A conventional insulated gate semiconductor device, for example, disclosed in U.S. Pat. No. 6,737,705 corresponding to JP-A-2001-308327, has an element region where a P-type base layer is formed on an N-type drift layer and divided by trenches into channel portions and floating portions. Each trench penetrates the base layer and reaches the drift layer.
An emitter region is formed in the channel portion but is not formed in the floating portion. The emitter region is in contact with a side surface of the trench in the channel portion. The channel portions and the floating portions are repeatedly arranged in a predetermined pattern.
In general, a P-type diffusion layer (i.e., so-called P-well) is formed on the periphery of the element region. The depth of the diffusion layer is greater than the depth of the floating portion. The diffusion layer is located close to the end of the trench in the length direction of the trench to reduce electric field concentration on the end of the trench.
However, as the diffusion layer is located closer to the end of the trench, it is more difficult to allow the floating portion to electrically float with respect to the diffusion layer. In contrast, as the diffusion layer is located farther away from the end of the trench, breakdown voltage of the element decreases due to an increase in the electric field concentration on the end of the trench.